A phase locked loop (PLL) is a closed-loop feedback control system maintaining a generated signal in a fixed phase relationship to a reference signal, and is widely used in electronic devices, such as radio receivers and transmitters. FIG. 1 is a block diagram illustrating schematically the different parts of a typical PLL. The PLL 1 generally comprises a phase detector 2, a filter section 3 and a voltage-controlled oscillator (VCO) 4. There may further be a divider 5 or a divide-by-N counter in the feedback path in order to make the output of the PLL a multiple of a reference signal. The phase detector 2 receives a reference signal Sref and an oscillator signal SOSC as inputs, and its function is to compare the phases of these signals and cause the filter section 3 to change a control voltage in order to raise or lower the frequency (and hence the phase) of the oscillator 4. The output from the phase detector 2 is a control signal or error signal Serror, which is a function of the phase difference between the input reference signal Sref and the oscillator signal SOSC. The filter section 3 comprises an integrator for accomplishing the speeding up or slowing down of the oscillator frequency. The integrator is conventionally implemented using a charge pump and a loop filter capacitor for low-pass filtering the output control signal.
In microelectronics, the voltage controlled oscillator 2, the divider 5 and the phase detector 2 are often integrated on a single chip and the filter section 3 or loop filter is sometimes integrated on chip and sometimes placed externally to the chip as discrete components. An exemplary prior art layout of the filter section 3 or loop filter is shown in FIG. 2. The analog loop filter 3 comprises analog components such as resistors R and capacitors C. The loop filter 3 performs an integration function, which is as mentioned above often implemented by means of a charge pump and a loop filter capacitor. Such loop filter capacitors generally need to be rather large and require therefore a substantial area on the chip.
There are several drawbacks related to such loop filters. The chip area required if implementing the loop filter on a single chip is relatively large, mainly due to the above mentioned loop capacitors. If placed outside the chip as separate components, it adds to the overall bill of material (BOM). Further, if a frequency modulation is added to the voltage controlled oscillator, care has to be taken to compensate for the loop filter dynamics, as is well known within the field. Analog components have some tolerances and it is often tedious and time consuming to trim a loop filter to the required application, entailing for example measurements of the loop filter response and calibration of the frequency modulated signal.
It would thus be desirable to provide an improved phase locked loop circuit, having a reduced size and in which the calibration of the loop filter dynamics is facilitated.